Rapid prototyping of a sytem on chip:
A multimode navigation system processor
Madhav P. Desai
Miércoles 20 de Febrero de 2019, 15:00
Aula Polivalente 2
Escuela Politécnica Superior
Universidad CEU San Pablo
Descripción de la actividad:
Ponencia sobre el diseño de un SoC (CPU, RAM y coprocesador) de bajo consumo para la implementación de un sistema de navegación multimodal mediante el uso del lenguaje de alto nivel AHIR.
The complexity of SoCs (System-On-Chip) requires the use of easy-to-use automated design tools that enable the fast prototyping and implementation of electronics systems. The toolchain AHIR has proved to be an adequate means to face the design of complex systems. For instance, systems to perform the analysis of ECG signals, or even a 32-bit RISC microprocessor have been successfully designed with the tool.
In this talk we address the complete design of a complex digital SoC able to decode multimode navigation system signals through the tool AHIR. The SoC is composed of a CPU, a coprocessor and a memory block. The system specifications impose a low-power consumption, targeting embedded systems, and a high-performance processing capability. A customized architecture is used in order to comply with such constraints.
The use of a fast design tool allows a dramatic reduction of time to market.
Sobre el ponente
Madhav P. Desai holds a degree in Electrical Engineering from IIT Bombay and a PhD degree from University of Illinois in Urbana-Champaign. During the period 1992-1996 he was with the Semiconductor Engineering Group of Digital Equipment Corporation in Hudson, MA, where he worked as Principal Engineer developing two of the fastest CMOS microprocessors in history. Currently, he is a Full Professor at the Department of Electrical Engineering, Indian Institute of Technology, Bombay. His research lines cover VLSI design, circuits and systems, and combinatorial algorithms.
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Escuela Politécnica Superior. Universidad San Pablo CEU / Departamento de Tecnologías de la Información