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WORKSHOP ON FAST DESIGN OF DIGITAL SYSTEMS 20 and 21 February 2019 Sala Polivalente 1 Escuela Politécnica Superior, Universidad San Pablo CEU Campus de Montepríncipe – Alcorcón |
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Sponsored by IEEE Circuits and Systems Society – Spanish Section
http://www.cass-ieeespain.org/
| AGENDA | |
| 20 February
10:00-10:15
10:15-11:00
11:00-11:15 11:15-13:30
15:00-17:00 |
· Welcome message (Gabriel Caffarena, USP-CEU) · New trends in FPGA and configurable Soc design (Ricardo Gómez Galarza, AVNET-Silica) · Coffee break · Lab session I: Introduction to AHIR toolchain (Madhav P. Desai, IIT-Bombay) · Rapid prototyping of a sytem on chip: A multimode navigation system processor (Madhav P. Desai, IIT-Bombay) |
| 21 February
9:30-11:00
11:00-11:15 11:15-13:30 |
· Lab session II: More on AHIR toolchain (Madhav P. Desai, IIT-Bombay) · Coffee break · Lab session III: Signal processing case study (Madhav P. Desai, IIT-Bombay) |
| SUMMARY | The workshop is aimed at researchers and hardware engineers and covers the fast design of digital systems (e.g. FPGA, ASIC) with the electronic design tool AHIR. AHIR enables the hardware compilation of a circuit description. The input entry is a high-level programming language and the output is fully functional VHDL. All sessions are composed of theory and practice. Examples will be tested on FPGA boards. In day 1 there will be an overview on the latest FPGA trends provided by AVNET-Silica Engineers. |
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SPEAKERS SHORT BIOGRAPHY |
Madhav P. Desai holds a degree in Electrical Engineering from IIT Bombay and a PhD degree from University of Illinois in Urbana-Champaign. During the period 1992-1996 he was with the Semiconductor Engineering Group of Digital Equipment Corporation in Hudson, MA, where he worked as Principal Engineer developing two of the fastest CMOS microprocessors in history. Currently, he is a Full Professor at the Department of Electrical Engineering, IIT Bombay. His research covers VLSI design, circuits and systems, and combinatorial algorithms. Avnet Silica is the European semiconductor specialist division of Avnet Inc., one of Gabriel Caffarena is Associate Professor at University CEU-San Pablo. His research focuses on hardware acceleration of signal processing algorithms. |
The workshop is free but it is necessary to register due to limited seating capacity. Please send an email to gabriel.caffarena@ceu.es
(Professor Madhav P. Desai will mainly talk in English, but he is also fluent in Spanish)
